A Review on Leakage Power Reduction Techniques at 45nm Technology

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications like laptops and mobiles. Since these devices remain in stand-by mode significantly longer than in active mode, their stand-by current, and not t...

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Bibliographic Details
Main Authors: Kumar, N. Praveen, Charles, B. Stephen, Sumalatha, V.
Format: Conference Proceeding
Language:English
Subjects:
Standby Power
Sub-threshold
Tunneling
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Summary:There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications like laptops and mobiles. Since these devices remain in stand-by mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by current drawn by such devices especially at nanometer regime. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper we presented various techniques to reduce the standby power at 45nm technology.
ISSN:2214-7853
2214-7853
DOI:10.1016/j.matpr.2015.10.074