A facile approach to design truncated multiplier based on HSCG-SCG CSLA adder

• Main Authors: Penchalaiah, Usthulamuri, Siva Kumar, VG
• Format: Conference Proceeding
• Language: English
• Subjects: CLA; FIR filter; HSCG-SCG; Signal Processing; Truncated multiplier; VLSI
• ISSN: 2214-7853; 2214-7853
• DOI: 10.1016/j.matpr.2021.02.629

•Novel approach for Signed, Unsigned truncated multiplier based on HSCG-SCG CSLA Adder.•Proposed work attempts to replace adders to HSCG-SCG method.•This proposed design will reduce the number of logic gates in arithmetic operation of multiplication, addition. Applications such as audio processing, signal processing, SDR and such will work with elite efficiency in recent decades of technology development, in the context of sign preparation and image handling, and are extremely convenient as far as the area is concerned. There may be more signal noises and inconsistencies in digital signal processing units which use all categories of gadgets. In contrast, these applications consume greater areas in practical deployment in VLSI due to the arithmetic operation of the Adders and Multiplier design. Here, the proposed advanced method intends to design a novel outlook of FIR filter by replacing adders and multipliers to the proposed signed and unsigned Truncation Multiplier and HSCG-SCG adders. In this approximate partial reduction of products, the structure of truncation multiplier will have a number of the adders. This proposed work also attempts to replace these adders to HSCG-SCG method. This proposed design will reduce the number of logic gates in arithmetic operation of multiplication, addition and also proves efficient in signed and unsigned methods of signal processing applications.