Low Power Single Bit Cache Memory Architecture

• Main Authors: Agrawal, Reeya, Kumar, Manish
• Format: Conference Proceeding
• Language: English
• Subjects: Current Mode Sense Amplifier (CMSA); Sense amplifier (SA); Single Bit SRAM CMSA Architecture (SBSCMSA); Single Bit SRAM VMSA Architecture (SBSVMSA); Static random access memory (SRAM); Voltage Mode Sense Amplifier (VMSA); Write driver circuit (WDC)
• ISSN: 2214-7853; 2214-7853
• DOI: 10.1016/j.matpr.2021.02.725

A quantitative and yield analysis of single bit cache memory architecture has been analyzed. A single bit cache memory architecture is made up of a write driver circuit, static random access memory cell, and sense amplifiers such as voltage mode sense amplifier and a current-mode sense amplifier. Apart from it, the power reduction technique has been applied over different blocks of single bit cache memory architecture such as sense amplifiers and static random access memory cell, to optimize the power consumption of the circuit. To check the robustness of the circuit monte carlo simulation and process corner simulation also have been done. The conclusion arises that single bit cache memory architecture having volatge mode sense amplifier with forced stack technique over static random access memory in an architecture consumes the lowest power (9.108 µW) with an area of 6.613 × 30.48 mm2.