Calibration of offset via bulk for low-power HfO2 based 1T1R memristive crossbar read-out system

Neuromorphic RRAM circuits typically need currents of several mA when many binary memristive devices are activated at the same time. This is due to the low resistance state of these devices, which increases the power consumption and limits the scalability. To overcome this limitation, it is vital to...

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Bibliographic Details
Published in:Microelectronic engineering 2018-10, Vol.198, p.35-47
Main Authors: Mohan, C., Camuñas-Mesa, L.A., Vianello, E., Periniolla, L., Reita, C., de la Rosa, J.M., Serrano-Gotarredona, T., Linares-Barranco, B.
Format: Article
Language:English
Subjects:
Calibration
Crossbar
Memristor
Nano-CMOS
Neuromorphic
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Summary:Neuromorphic RRAM circuits typically need currents of several mA when many binary memristive devices are activated at the same time. This is due to the low resistance state of these devices, which increases the power consumption and limits the scalability. To overcome this limitation, it is vital to investigate how to minimize the amplitude of the read-out inference pulses sent through the crossbar lines. However, the amplitude of such inference voltage pulses will become limited by the offset voltage of read-out circuits. This paper presents a three-stage calibration circuit to compensate for offset voltage in the wordlines of a memristor-array read-out system. The proposed calibration scheme is based on adjusting the bulk voltage of one of the input differential pair MOSFETs by means of a switchable cascade of resistor ladders. This renders the possibility to obtain calibration voltage steps less than 0.1 mV by cascading a few number of stages, whose results are only limited by mismatch, temperature, electrical noise and other fabrication defects. The system is built using HfO2-based binary memristive synaptic devices on top of a 130-nm CMOS technology. Layout-extracted simulations considering technology corners, PVT variations and electrical noise are shown to validate the presented calibration scheme. [Display omitted] •HfO2 based 1T1R crossbar integrated on top of a 130-nm CMOS chip where form, erase, write and read operations are carried out•A 3-stage DC offset calibration is done via bulk of the opamp, used in buffer configuration across the wordlines of crossbar•Calibration scheme aids low-amplitude read-outs & gives scope for low power consumption and increased scalability•A full-digital control of the calibration scheme & current biases for the opamps
ISSN:0167-9317
1873-5568
DOI:10.1016/j.mee.2018.06.011