Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection ci...

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Bibliographic Details
Published in:Microelectronics 2006-06, Vol.37 (6), p.526-533
Main Authors: Semenov, O., Sarbishaei, H., Axelrad, V., Sachdev, M.
Format: Article
Language:English
Subjects:
Electrostatic discharge (ESD)
ESD robustness
Gate triggering
Substrate triggering
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Summary:As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements.
ISSN:1879-2391
1879-2391
DOI:10.1016/j.mejo.2005.07.019