Designing efficient QCA logical circuits with power dissipation analysis

Recently reported QCA logical and arithmetic designs have completely disregarded the power consumption issue of the circuits. In this paper, a comprehensive power dissipation analysis as well as a structural analysis over the previously published five-input majority gates is performed. During our ex...

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Bibliographic Details
Published in:Microelectronics 2015-06, Vol.46 (6), p.462-471
Main Authors: Sheikhfaal, Shadi, Angizi, Shaahin, Sarmadi, Soheil, Hossein Moaiyeri, Mohammad, Sayedsalehi, Samira
Format: Article
Language:English
Subjects:
Dissipated power
Even parity generator
Five-input majority gate
Nanoelectronics
Power analysis
Quantum-dot cellular automata
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Summary:Recently reported QCA logical and arithmetic designs have completely disregarded the power consumption issue of the circuits. In this paper, a comprehensive power dissipation analysis as well as a structural analysis over the previously published five-input majority gates is performed. During our experimentations, we found that these designs suffer from high power consumption and also structural weaknesses. Therefore, a new ultra-low power and low-complexity five-input majority gate is proposed. For examining our presented design in large array of QCA structures even parity generators, as instances of logical circuits with different lengths up to 32 bits are presented. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from implementation requirements and power consumption aspects. QCADesigner tool is used to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool.
ISSN:1879-2391
1879-2391
DOI:10.1016/j.mejo.2015.03.016