High throughput implementation of SHA3 hash algorithm on field programmable gate array (FPGA)

• Published in: Microelectronics 2019-11, Vol.93, p.104615, Article 104615
• Main Authors: El Moumni, Soufiane, Fettach, Mohamed, Tragha, Abderrahim
• Format: Article
• Language: English
• Subjects: FPGA device; High-speed implementation; SHA3 hash function
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2019.104615

Cryptographic hash function is an essential element in sensitive communications, such as banking, military and health. It ensures secure communication by checking data integrity, storing passwords and other important roles. Keccak hash function (i.e. SHA3) is the best one in terms of resistance against recent cryptanalysis attacks as well as of hardware performance. However, an efficient improvement in terms of hardware performance is always needed, such as increasing speed or decreasing area consumption. In this paper, we have focused on improving the speed (throughput) of Keccak hash algorithm by proposing a new design which is based on decreasing the number of clock cycles needed to produce a hash value. Consequently, we could achieve 33.35 Gbps as a highest achieved throughput. However, a decrease in terms of maximum frequency has been noticed. Our design has been implemented in Xilinx Virtex5 and Virtex6 FPGA device, and has been compared to recent published implementations.