Performance analysis of clock pulse generators and design of low power area efficient shift register using multiplexer based clock pulse generator

• Published in: Microelectronics 2020-11, Vol.105, p.104891, Article 104891
• Main Authors: Murugasami, R., Ragupathy, U.S.
• Format: Article
• Language: English
• Subjects: Clock pulse generator; Multiplexer; Power consumption; Shift register; Transistor count
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2020.104891

Shift registers are the essential elements that are capable of storing and transmitting the data in sequential mode in digital circuits. It consists of D flip-flops, which are connected in a successive manner and share the common clock pulse applied to each Flip-flop. However, the clock distribution network consumes the major portion among the whole power consumption. In this paper a novel clock pulse generation scheme, called as Multiplexer based Clock Pulse Generator (MCPG) is proposed to minimize the power consumption and reduce the silicon area occupation of the shift register by reconstructing the clock distribution network using MCPG. It generates multiple non overlapped clock pulses with minimum power utilization, less area and also resolves the inequality between arrival of clock pulse and data to the consecutive Flip-flops at different time. The proposed clock distribution method reduce area and overall power consumption up to 22% and 31% respectively, compared with shift registers implemented using conventional clocking methods. The optimized MCPG with Conditional Pass Logic Dynamic D Flip-flop(CPLDDFF) is also implemented in 256-bit arrayed shift register via an 8- bit Serial In Serial Out(SISO) sub shift register, save power up to 12%. The proposed system is realized using SPICE with CMOS 0.13 μm technology.