High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects

• Published in: Microelectronics 2021-01, Vol.107, p.104941, Article 104941
• Main Authors: Jadav, Sunil, Tayal, Shubham, Chandel, Rajeevan, Vashishath, Munish
• Format: Article
• Language: English
• Subjects: Asymptotic; Characteristic impedance; Current mode; Elmore delay model; Sakurai delay model
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2020.104941

This work proposes a mathematical delay models for global VLSI interconnects using normalized asymptotic value of characteristic impedance of RLC interconnected line. In the proposed Model (R0C0) the delay of RLC interconnects line is formulated by incorporating the line inductance in terms of effective impedance. The earlier simple RC interconnect models results in a significant error in delay estimation in long interconnects. Due to this analogy the non-ideal effect of inductive behaviour at high frequencies and scaled technologies such as ringing, spikes overshoot and undershoot can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. Step response analysis of the proposed model is validated with the existing literature and found to be superior. Using this approach the results for both the signaling technique i.e. voltage and current mode signaling are found in close agreement between analytical and simulation for long interconnect lines.