Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design

• Published in: Microelectronics 2023-02, Vol.132, p.105699, Article 105699
• Main Authors: Dai, Chenghu, Du, Yuanyuan, Shi, Qi, Wang, Ruixuan, Zheng, Hao, Lu, Wenjuan, Peng, Chunyu, Hao, Licai, Lin, Zhiting, Wu, Xiulong
• Format: Article
• Language: English
• Subjects: Bit-line leakage current; Integrated circuit; Lower power; Self-compensation circuit; SRAM
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2023.105699

For low voltage CMOS static random access memory (SRAM) cells, the leakage current on bit-lines will slow down the reading operation and even lead to error reading. Herein we report a 4B4C circuit composed of 8T SRAM arrays, four bit-lines and four coupling capacitors to track and compensate the bit-line leakage current (BLLC). The assistant bit-lines are used to control the connection of capacitors. The coupling capacitors are used to compensate voltage losses caused by the BLLC, and improve the maximum tolerable current from primary bit-line. The timing diagram and output waveforms verify the compensatory effects of coupling capacitors. The 4B4C circuit shows fast reading operation and increases the maximum tolerable leakage current to 17.8 times compared with conventional circuit at FS process corner. The 4B4C circuit can keep 100% correct reading till 200 μA from Monte Carlo simulations. The 4B4C circuit enhances SRAM reading reliability and shows huge potential in very-large scale memory arrays.