A fast-convergence, tree-structured, fully-parallel digital background timing mismatch calibration method for four-channel TIADC based on perfect reconstruction filter bank

• Published in: Microelectronics 2023-11, Vol.141, p.105978, Article 105978
• Main Authors: Liu, Yu, Zhang, Zhenwei, Lang, Lili, Liu, Haijing, Wu, Xufan, Dong, Yemin
• Format: Article
• Language: English
• Subjects: Correlation-based estimation; Fully-digital background calibration; Perfect reconstruction filter bank; Time-interleaved ADC; Variable step-size LMS algorithm
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2023.105978

This paper presents a fully-digital background timing mismatch calibration method for four-channel time-interleaved analog-to-digital converter (TIADC). Based on three improved dual-channel perfect reconstruction filter banks (PRFBs), the proposed method for correcting timing mismatch adopts the tree-structured four-channel PRFB. Unlike the direct four-channel PRFB, the improved structure utilizes fewer filter taps to achieve higher filter performance, making it suitable for real-time background calibration. Furthermore, timing mismatch is estimated by performing correlation calculations on the outputs of sub-channels with the variable step-size least mean squares (LMS) algorithm, being approximately eight times faster than the fixed step-size LMS algorithm. Our method verified by a 12-bit 3 GS/s TIADC test platform indicates that the spurs caused by the timing mismatch for single-tone and multi-tone signals can be effectively suppressed, close to 35 and 40 dB, respectively. The evaluation results on the Xilinx Vertix-7 VC707 platform indicate that the proposed method reduces FPGA hardware resources consumption by nearly 40% compared to the foreground pre-calibration method.