VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

• Published in: Microprocessors and microsystems 2016-11, Vol.47, p.466-485
• Main Authors: Chouliaras, V.A., Stevens, D., Dwyer, V.M.
• Format: Article
• Language: English
• Subjects: Configurable VLIW architectures; Embedded microprocessors; Field-programmable gate array design; Hardware/software interface; RTL implementation; Standard-cell design
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2016.07.010

We discuss VThreads, a novel VLIW CMP with hardware-assisted shared-memory Thread support. VThreads supports Instruction Level Parallelism via static multiple-issue and Thread Level Parallelism via hardware-assisted POSIX Threads along with extensive customization. It allows the instantiation of tightly-coupled streaming accelerators and supports up to 7-address Multiple-Input, Multiple-Output instruction extensions. VThreads is designed in technology-independent Register-Transfer-Level VHDL and prototyped on 40  nm and 28  nm Field-Programmable gate arrays. It was evaluated against a PThreads-based multiprocessor based on the Sparc-V8 ISA. On a 65  nm ASIC implementation VThreads achieves up to x7.2 performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and ∼13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores, VThreads demonstrates a post-route (statistical) power reduction between 65% and 57% at an area increase of 1.2%–10% for 1–8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support.