Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation

• Published in: Microprocessors and microsystems 2022-10, Vol.94, p.104659, Article 104659
• Main Authors: Anil Kumar, Uppugunduru, Guturu, Sahith, Ahmed, Syed Ershad
• Format: Article
• Language: English
• Subjects: Approximate compressor; Approximate computing; Integer motion estimation; Sum of absolute difference
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2022.104659

Integer motion estimation performs a pivotal role in achieving video compression by exploiting the temporal redundancy of video sequences. However, the motion estimation’s computational complexity is huge and requires much computational power in real-time. On the other hand, portable mobile devices which operate on battery power have minimal computational capabilities. Since the video encoding can tolerate error up to a specific limit, the hardware complexity can be reduced by approximating the motion estimator’s fundamental modules. The major contributor to the power consumption in the motion estimator is the sum of the absolute difference (SAD) module. This paper presents SAD architectures implemented using new approximate 8:2 compressors to reduce the computational complexity. Thus, leading to a reduction in the hardware complexity and power consumption while maintaining the coding efficiency. Our proposed approximate SAD architecture achieves up to 56.7% and 49.8% savings in power compared to exact compressor-based SAD architectures and existing approximate SAD architectures respectively.