Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital

• Published in: Microprocessors and microsystems 2024-03, Vol.105, p.105021, Article 105021
• Main Authors: León, Daniel, Fabero, Juan Carlos, Clemente, Juan A.
• Format: Article
• Language: English
• Subjects: COTS; Fault injection; RISC-V; Soft error; VeeR EH1
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2024.105021

This article studies the ISA-extension and application-specific soft error sensitivity of the RISC-V VeeR EH1 commercial processor core from Western Digital. To this end, a modified VeeRwolf SoC from Chips Alliance was deployed in a Digilent Nexys-A7 FPGA. Then, a fault injection platform was created for injecting soft errors in all architectural and micro-architectural registers of the VeeR EH1, without modifying the original processor core, when executing a set of commonly used space-related algorithms. Errors were categorized according to the consequences that they had on the normal execution of the processor, as well as to the unit of the core they were injected in. By changing compiling targets, four different combinations of RISC-V ISA extensions were also tested and compared, in the same processor IP, for a typical dot product algorithm, a hyperspectral imaging difference calculation and a SHA-256 hash. Experimental results will show how, for each one of these three case studies, the functionally equal binaries issued when compiling these programs using different ISA extensions are affected in different ways by error injections, opening the possibility to selectively compile functions based on a desired reliability/speed factor. The results additionally identify the specific units and subUnits within the processor’s structure that have been affected, pinpointing the exact element where the bitflip occurred, after detecting an error.