UIS performance and ruggedness of stand-alone and cascode SiC JFETs

• Published in: Microelectronics and reliability 2020-11, Vol.114, p.113803, Article 113803
• Main Authors: Agbo, S.N., Ortiz Gonzalez, J., Wu, R., Jahdi, S., Alatise, O.
• Format: Article
• Language: English
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2020.113803

In this paper the ruggedness of stand-alone and cascode SiC JFETs is evaluated under single and repetitive unclamped inductive switching (UIS). The impact of the JFET gate resistance, avalanche current and temperature are evaluated. The results show that the avalanche characteristics are strongly affected by the peak avalanche current and the JFET gate resistance. Due to the absence of an insulating gate, there is significant JFET gate current during avalanche. This gate leakage current plays a fundamental role on the reduced performance under repetitive UIS of SiC cascode JFETs compared with stand-alone SiC JFETs. •SiC Cascode JFETs present atypical unclamped inductive switching (UIS) performance at high case temperature.•Stand-alone SiC JFETs have been evaluated under UIS.•Experiments and simulations have been performed.•Gate current and JFET gate resistance play a fundamental role on the cascode performance under UIS.