A programmable checker for automated 2.5D/3D IC latch-up verification and hot junctions detection

• Published in: Microelectronics and reliability 2021-09, Vol.124, p.114310, Article 114310
• Main Authors: Medhat, Dina, Dessouky, Mohamed, Khalil, DiaaEldin
• Format: Article
• Language: English
• Subjects: 2.5D; Assembly; Die; EDA; Hot junction; Latch-up; Reliability; TSV; Verification
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2021.114310

Many challenges accompany the use of three-dimensional (3D) integrated circuits (ICs). Some of these challenges are design-related, while others are verification-related. In this paper, we focus on verification issues; more precisely, on advanced layout physical verification tasks, such as advanced latch-up design rule checks and candidate hot junction detection. We explain the differences and additional challenges as compared to conventional two-dimensional (2D) IC verification. We introduce a programmable checker to automate these verification challenges for complete 3D IC designs. The checker differentiates between external and internal inputs/outputs from the assembly level without using layout markers on the die level. It checks external latch-up design rules using a topology-aware analysis, and checks mixed voltage latch-up design rules using a voltage-aware analysis. It also detects candidate hot junctions, because their existence can cause damage if voltage rises too high and current is not sufficiently limited. A design is used to illustrate the different type of checks, and demonstrate how to set up required input constraints, share captured results/violations, and effectively debug results to overcome potential design weaknesses. •2.5D/3D IC latch-up•2.5D/3D IC hot junction detection•Automated verification•Calibre PERC