Stacked Dual Oxide Nano MOS Parameter Optimization For 3-D IC Realization

With advent of nano technology, a threshold voltage of a MOSFET can be engineered. In order to increase the packing density of the transistors on multicore processor/SOC with FPGA and processor, and 3-D IC realization, stacking of materials are necessary with lesser parasites like capacitance, volta...

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Bibliographic Details
Published in:Procedia materials science 2015, Vol.10, p.441-445
Main Authors: Sathyanarayana, Ch, Rao, S.P. Venu Madhava, Charyulu, EVLN Ranga
Format: Article
Language:English
Subjects:
bandgap
dielectric constant
electron affinity
Stack capacitance
stacked material
thickness
TiN
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Summary:With advent of nano technology, a threshold voltage of a MOSFET can be engineered. In order to increase the packing density of the transistors on multicore processor/SOC with FPGA and processor, and 3-D IC realization, stacking of materials are necessary with lesser parasites like capacitance, voltage drop etc. In this paper, we present Silicon as a base material and metal like TiN (Titanium Nitride) as top layer is analyzed. The parameters of the different stacked materials are optimized to achieve required CStack (Stack Capacitance) and VTh. It is used explore the behavior of dual oxide MOS parameters like oxide material, electron affinity, bandgap, dielectric constant, and thickness.
ISSN:2211-8128
2211-8128
DOI:10.1016/j.mspro.2015.06.079