Improved SOI LDMOS performance by using a partial stepped polysilicon layer as the buried layer

• Published in: Materials science in semiconductor processing 2019-02, Vol.90, p.7-12
• Main Authors: Guo, Jingwei, Hu, Shengdong, Huang, Ye, Yuan, Qi, Yang, Dong, Yang, Ling, You, Liang, Yu, Jianyi
• Format: Article
• Language: English
• Subjects: Breakdown voltage; LDMOS; Self-heating effect; Specific on-resistance; Stepped buried layer
• ISSN: 1369-8001; 1873-4081
• DOI: 10.1016/j.mssp.2018.09.028

A novel SOI LDMOS with a stepped polysilicon compound buried layer (SP-CBL) is proposed in this paper. In the SP-CBL SOI LDMOS, a stepped polysilicon layer is introduced into the buried layer. Firstly, SP-CBL brings in two new electric field peaks and modulates the electric field of drift region and obviously promotes the breakdown voltage (BV). Secondly, SP-CBL reduces the thickness of the top buried oxide layer, and the doping concentration of the drift region is thus increased according to the RESURF condition. The specific on-resistance (Ron,sp) is reduced. In addition, the polysilicon conducts heat more efficiently than SiO2, relieving the self-heating effect to some extent. The effects of critical structure parameters on the device performances are investigated. Ultimately, compared with the partial compound buried layer structure (P-CBL SOI LDMOS), BV of SP-CBL SOI LDMOS is enhanced by 13.7% and Ron,sp is reduced by 15% at the same device dimension, and the maximum temperature is dropped by 7.2 K at the power of 1 mW/μm. Compared with the conventional SOI LDMOS (C-SOI LDMOS), BV is enhanced by 66.3%, Ron,sp is reduced by 52.4%, and temperature is depressed by 11.4 K.