Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis

• Published in: Materials science in semiconductor processing 2021-10, Vol.133, p.105966, Article 105966
• Main Authors: Baral, Kamalaksha, Singh, Prince Kumar, Kumar, Gautam, Singh, Ashish Kumar, Tripathy, Manas Ranjan, Kumar, Sanjay, Jit, Satyabrata
• Format: Article
• Language: English
• Subjects: 6T-SRAM; CMOS inverter; Gaussian doping; Noise margin; Stacked oxide CG-JAM; Transient analysis
• ISSN: 1369-8001; 1873-4081
• DOI: 10.1016/j.mssp.2021.105966

This article analyses the effect of ion implantation on electrical and circuit-level characteristics of stacked oxide cylindrical gate (CG) junctionless accumulation mode (JAM) MOSFET. Ion implantation and subsequent annealing create a Gaussian type doping profile inside the channel. A detailed study of electrical characteristics such as: drain current, threshold voltage, Ion/Ioff, transconductance (gm), output conductance (gd), capacitances (Cgs, Cgd, Cgg), unit gain frequency (fT), transit time (τ), transconductance frequency product (TFP) and gain bandwidth (GBW) product have been performed. Further, an inverter has been designed with a complimentary p-MOSFET and a lookup table-based Verilog-A model has been generated for the same. Various dc and transient parameters such as noise margin, rise time, fall time propagation delay, voltage overshoot, average current, and power dispassion have been analyzed in detail. Henceforth, a 6 T SRAM cell has been implemented with ion-implanted stacked oxide CG-JAM MOSFET and read margin, write margin, access time and N-curve analysis have been performed. Various figures of merits (FOMs) have also been studied for the device at the circuit level. All the device simulations have been performed using a 3-D TCAD tool from COGENDA. Verilog-A model-based circuit simulations have been done in the Cadence-Virtuoso platform. •DC and RF characteristics of stacked oxide Ion Implanted cylindrical gate Junctionless accumulation mode MOSFET have been studied for the first time.•A look-up-table based Verilog-A model has been implemented for the device.•CMOS inverter and 6 T SRAM cell has been implemented and analyzed with the help of the Verilog-A model.