Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

• Published in: Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Accelerators, spectrometers, detectors and associated equipment, 2017-03, Vol.847, p.93-98
• Main Authors: Zeng, Huiming, Wei, Tingcun, Wang, Jia
• Format: Article
• Language: English
• Subjects: ASIC; CdZnTe detector; Front-end readout; High-Z circuit; The linearity of conversion gain
• ISSN: 0168-9002; 1872-9576
• DOI: 10.1016/j.nima.2016.11.045

A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35µm CMOS process with a die size of 2.60mm×3.53mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e−+16.3e−/pF with a power consumption of 4mW and achieves a conversion gain of 87mV/fC with a nonlinearity of