A multi-channel PCI express readout board for fast readout of large pixel detectors

• Published in: Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Accelerators, spectrometers, detectors and associated equipment, 2019-04, Vol.924, p.279-281
• Main Authors: Gabrielli, A., Alfonsi, F., Balbi, G., D’Amen, G., Falchieri, D., Giangiacomi, N., Travaglini, R.
• Format: Article
• Language: English
• Subjects: [formula omitted]-LUP; Data acquisition circuits; FELIX; Readout system
• ISSN: 0168-9002; 1872-9576
• DOI: 10.1016/j.nima.2018.06.080

Recently the ATLAS Pixel Detector at CERN has been upgraded by inserting an additional layer of pixels, the Insertable B-Layer (IBL). In addition, the off-detector readout electronics of the other layers that composed the Pixel Detector (the B-Layer, the Layer 1, the Layer 2 and the Disks) were updated using the IBL readout boards. The system has been updated, one layer at a time, giving priority to the next critical layer as the luminosity and level-1 trigger frequency increased. Hence, after IBL, the first critical layer was the Layer 2, then the Layer 1 and finally the B-Layer and the Disks. Eventually, after the technical stop in 2018 the entire ATLAS Pixel Detector will share the same off-detector readout electronics. In parallel with the commissioning of the upgrade of the current ATLAS Pixel Detector we have designed and fabricated a new readout electronic board to address the requirements of the LHC Phase-2 upgrade. Two batches of prototypes of a Peripheral Component Interconnect Express (PCIe) Gen. 2 boards have been designed and fabricated, the second being a patched version of the first. The first batch was composed of two boards, called Pixel ReadOut Driver (Pixel_ROD) and the second batch was made of five cards called π-LUP. All the boards feature many of the input–output ports and interfaces to address the requirements of the future front-end electronics being developed for the Large Hadron Collider (LHC) Phase-2 upgrade. Thus, the current VERSABUS Module Eurocard (VME) bus will be replaced with the PCIe bus to accommodate the huge increase of throughput (data to be transferred to the DAQ). In this new scenario, the GigaBit Transceiver (GBT) and Aurora protocols are compatible with our boards and the GBTx and RD53A chips will be the first components to be interfaced with. Some laboratory results and measurements are presented here. •Off-detector readout boards define a huge challenge for the LHC Phase-2 upgrade.•COTS are ever more replacing custom electronics in off-detector readout systems.•Firmware for latest generation FPGAs is a big issue to design and maintain.•PCI-express bus is a proposal for the LHC readout upgrade.