High Speed and Low Power Implementation of AES for Wireless Sensor Networks

• Published in: Procedia computer science 2018, Vol.143, p.736-743
• Main Authors: Thangarajan, Sreenath, Bhaaskaran, V S Kanchana
• Format: Article
• Language: English
• Subjects: AES; Cryptography; High-Speed Cryptography Circuits; Low Power Cryptography Design; Pipelining Architectures
• ISSN: 1877-0509; 1877-0509
• DOI: 10.1016/j.procs.2018.10.440

In the recent years, data security has become the biggest concern due to the increasing number of connected devices. Hence, cryptography has become vital for enhancing data security. Cryptography is a technique which converts the data into an unintelligible form. In applications such as the wireless sensor networks, it plays a major role since most of the data is transmitted over an insecure channel. Symmetric key cryptosystems play a major role in such applications, since they are lightweight and faster in operation. Power dissipation of the system is another major concern for such applications as they are battery-operated devices. In this paper, the power dissipation of the circuit is enhanced by trading off area and throughput. The power is minimized by the method of parallel processing the hardware along with reduced amount of redundant hardware. The power dissipation of the circuit for the proposed structure is presented to be 2.04 times less than that of existing parallel processing structures. The proposed architecture was implemented using the industry standard Cadence® Encounter SoC tools using TSMC180 technology library.