Area Efficient High Speed Approximate Multiplier with Carry Predictor

Multimedia and image processing applications, may tolerate errors in calculations but still generate meaningful and beneficial results. This work deals with a high speed approximate multiplier with TDM tree and carry prediction circuit. The modified multiplier utilizes an optimised TDM carry save tr...

Full description

Saved in:
Bibliographic Details
Published in:Procedia technology 2016, Vol.24, p.1170-1177
Main Authors: Sunny, Anju, Mathew, Binu K., Dhanusha, P.B.
Format: Article
Language:English
Subjects:
Approximate Carry Adder
Approximate Multiplier
Three Dimensional Reduction method
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Multimedia and image processing applications, may tolerate errors in calculations but still generate meaningful and beneficial results. This work deals with a high speed approximate multiplier with TDM tree and carry prediction circuit. The modified multiplier utilizes an optimised TDM carry save tree which reduces the device utilization on FPGA as well as the combinational path delay and power consumption. The proposed design is analyzed using the simulation and implementation results on Xilinx Spartan 3E family.
ISSN:2212-0173
2212-0173
DOI:10.1016/j.protcy.2016.05.072