Design and Analysis of 8 Bit Parallel Prefix Comparators Using Constant Delay Logic

Parallel Prefix Radix 2 8 bit Comparators using Constant Delay (CD) logic is presented in this paper. The constant delay logic pre discharges the output to zero logic and switches to a logic one through a critical path clocked PMOS transistor. CD logic operation is much faster than a dynamic logic c...

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Bibliographic Details
Published in:Procedia technology 2016, Vol.24, p.1178-1185
Main Authors: George, Amy Mariam, Chandran, G. Jyothish
Format: Article
Language:English
Subjects:
Constant Delay Logic
Dynamic Logic
Parallel Prefix Comparators
Small Swing Dynamic Comparator
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Summary:Parallel Prefix Radix 2 8 bit Comparators using Constant Delay (CD) logic is presented in this paper. The constant delay logic pre discharges the output to zero logic and switches to a logic one through a critical path clocked PMOS transistor. CD logic operation is much faster than a dynamic logic circuit during its D-Q mode of operation. The comparator's architecture consists of two stages; where the first stage uses a pass transistor pre encoding circuitry for achieving low power consumption and the second stage employs a high performance dynamic-CD-static logic manner combination comparators. Design and simulation were carried out in Mentor Graphics ELDO Simulator using 180nm technology.
ISSN:2212-0173
2212-0173
DOI:10.1016/j.protcy.2016.05.074