Temperature assessment of Si1-xGex source/drain heterojunction NT-JLFET for gate induced drain leakage ‒ A compact model

• Published in: Superlattices and microstructures 2021-08, Vol.156, p.106961, Article 106961
• Main Authors: Thakur, Anchal, Dhiman, Rohit
• Format: Article
• Language: English
• Subjects: Gate–induced drain leakage; Junctionless transistor; L-BTBT; Short channel effects; SiGe Source/drain silicon NT JLFET
• ISSN: 0749-6036; 1096-3677
• DOI: 10.1016/j.spmi.2021.106961

In this paper, we have investigated the impact of temperature (T) and drain bias voltage (Vds) on gate induced drain leakage (GIDL) in SiGe Source/Drain heterojunction silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET). We developed a temperature dependent model for surface potential, electric field EZ, L-BTBT induced IGIDL and full drain current Ids using 2-D Poison equation with suitable boundary conditions. We have also examined impact of temperature (activation energy) and drain bias voltage (electric field) on L-BTBT induced IGIDL. It is found that the increase in drain bias voltage causes 31.1% rise in IGIDL and elevation in temperature has 29.4% increase in IGIDL. Furthermore, we have examined impact of temperature on transconductance (gm) and output conductance (gd). The results demonstrated that temperature and drain bias voltage has significant impact on SiGe S/D NTJLFET, however, it is considerably less than the NTJLFET. •A compact model of drain current and impact of temperature along with drain bias has been studied in SiGe source/drain heterojunction NTJLFET.•It is found that the increase in drain bias voltage cause 31.1% rise in IGIDL, however, elevation in temperature increase IGIDL by 29.4%.•The elevation in temperature results in reduced tunnelling width at channel-drain interface and it leads to earlier triggering of L-BTBT induced GIDL.•The higher drain voltage combined with higher temperature has more influence on the L-BTBT induced GIDL.