Emerging silicon-on-nothing (SON) devices technology

In this paper we explain the advantages of very thin layers (in the channel and in the BOX) of the silicon-on-nothing (SON) transistors. Electrical results are also presented, with gate length down to 38 nm, with a conduction channel thickness as thin as 9 and 5 nm. It is also demonstrated that SON...

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Bibliographic Details
Published in:Solid-state electronics 2004-06, Vol.48 (6), p.887-895
Main Authors: Monfray, S., Skotnicki, T., Fenouillet-Beranger, C., Carriere, N., Chanemougame, D., Morand, Y., Descombes, S., Talbot, A., Dutartre, D., Jenny, C., Mazoyer, P., Palla, R., Leverd, F., Le Friec, Y., Pantel, R., Borel, S., Louis, D., Buffet, N.
Format: Article
Language:English
Subjects:
BOX
CMOS architecture
Epitaxy
Fully depleted
Metal gates
Short-channel effects
SiGe
SOI
SON
Totally silicided gates
Tunnel
Ultra-thin Si-films
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Summary:In this paper we explain the advantages of very thin layers (in the channel and in the BOX) of the silicon-on-nothing (SON) transistors. Electrical results are also presented, with gate length down to 38 nm, with a conduction channel thickness as thin as 9 and 5 nm. It is also demonstrated that SON is better suited than bulk for accepting a metallic gate for low-voltage operation due to its intrinsic low threshold voltage. We have integrated midgap CoSi 2 metal gate by total gate silicidation on SON transistors with Si-conduction channel thickness down to 5 nm. Finally, we will analyse the ITRS’01 CMOS Roadmap and show that SON allows reaching the I on/ I off specifications down to the 32 nm node and approaching closely those for the 22 nm node, that is by far impossible with bulk.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2003.12.013