Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode

• Published in: Solid-state electronics 2004-10, Vol.48 (10), p.1987-1992
• Main Authors: Zhu, Shiyang, Yu, H.Y., Chen, J.D., Whang, S.J., Chen, J.H., Shen, Chen, Zhu, Chunxiang, Lee, S.J., Li, M.F., Chan, D.S.H., Yoo, W.J., Du, Anyan, Tung, C.H., Singh, Jagar, Chin, Albert, Kwong, D.L.
• Format: Article
• Language: English
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2004.05.045

Both P- and N-channel MOSFETs with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420 °C. PMOSFETs with PtSi S/D show excellent electrical performance of an I on/ I off∼10 7–10 8 and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi 2− x S/D have ∼3 orders of magnitude larger I off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the I on/ I off∼10 5 at low drain voltage. It can be attributed to the relatively higher barrier height ( Φ n) of DySi 2− x /n-Si than that of PtSi/p-Si ( Φ p) and the rougher DySi 2− x film. Adding a thin intermediate Ge layer (∼1nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed.