Planar double-gate SOI MOS devices: Fabrication by wafer bonding over pre-patterned cavities and electrical characterization

• Published in: Solid-state electronics 2007-02, Vol.51 (2), p.231-238
• Main Authors: Chung, T.M., Olbrechts, B., Södervall, U., Bengtsson, S., Flandre, D., Raskin, J.-P.
• Format: Article
• Language: English
• Subjects: Applied sciences; CMOS process; Compound structure devices; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Microelectronic fabrication (materials and surfaces technology); Planar double-gate MOSFET; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon-on-insulator; Transistors; Volume inversion; Wafer bonding
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2007.01.017

In this paper, a novel method for the fabrication of planar double-gate (DG) MOS devices is presented. Successfully fabricated single-gate and DG MOSFET devices on the same wafer have been fully characterized and their electrical performances compared. The planar DG devices were fabricated using wafer bonding over pre-patterned cavities. Preliminary electrical characterization results show that the built planar DG devices exhibit the expected theoretical performances. We will also show the flexibility of this method in fabricating other devices besides planar DG and the possibility of changing the various materials used for the buried insulator layer. It is demonstrated that this fabrication method is a very promising and viable method for future technology application in fabricating novel devices.