New EEPROM concept for single bit operation

A new 0.56 μm 2 dual-gate EEPROM transistor is presented in this paper. To optimize the cell layout, a new model based on previous work has been developed. This concept allows single bit memory operations with high density; new cell programming conditions has been defined to optimize electrical beha...

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Bibliographic Details
Published in:Solid-state electronics 2008-10, Vol.52 (10), p.1525-1529
Main Authors: Raguet, J.R., Laffont, R., Bouchakour, R., Bidal, V., Regnier, A., Mirabel, J.M.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
Design. Technologies. Operation analysis. Testing
Digital circuits
Dual gate
EEPROM
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
High density
Integrated circuits
Integrated circuits by function (including memories and processors)
Reliability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Single bit
Transistors
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Description
Summary:A new 0.56 μm 2 dual-gate EEPROM transistor is presented in this paper. To optimize the cell layout, a new model based on previous work has been developed. This concept allows single bit memory operations with high density; new cell programming conditions has been defined to optimize electrical behavior. Concept has been validated in an EEPROM standard technology from STMicroelectronics and allows a cell area reduction of above 50%. With appropriate potentials, the cell produces a programming window of 4 V. Moreover, this dual-gate transistor in static mode becomes an adjustable threshold voltage transistor which can be used in logic circuit or RFID applications.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2008.06.027