Evaluation of voltage vs. pulse width modulation and feedback during set/reset verify-programming to achieve 10 million cycles for 50nm HfO2 ReRAM

• Published in: Solid-state electronics 2014-01, Vol.91, p.67-73
• Main Authors: Higuchi, Kazuhide, Takeuchi, Ken, Iwasaki, Tomoko Ogura
• Format: Article
• Language: English
• Subjects: Cycling; Endurance; Program verify; ReRAM
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2013.09.013

•Evaluation of various set and reset verification methods for HfOx resistive memory.•The best combination to obtain 10 million cycles endurance was found.•Best combination of voltage increment for set and pulse width increment for reset.•A model to explain device wear-out by long pulses or high voltage is proposed. 50nm HfO2 resistive memory cells were measured by 6×6 verification variations to determine the optimal method to achieve 107 endurance and yield. The combination of pulse width incrementation during reset and pulse height modulation during set provided the most stable and highest cycling capability. Based on these results, a new conceptual model is proposed which combines the physical conduction model with direct tunneling, and provides a calculation method to predict resistance and explain degradation and reset failure. Furthermore, intermediate storing of programming information on a page basis is proposed in order to improve overall endurance.