Low voltage operation of GaN vertical nanowire MOSFET

• Published in: Solid-state electronics 2018-07, Vol.145, p.1-7
• Main Authors: Son, Dong-Hyeok, Jo, Young-Woo, Seo, Jae Hwa, Won, Chul-Ho, Im, Ki-Sik, Lee, Yong Soo, Jang, Hwan Soo, Kim, Dae-Hyun, Kang, In Man, Lee, Jung-Hee
• Format: Article
• Language: English
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2018.03.001

•GaN vertical nanowire MOSFET is fabricated by top-down approach.•Saturation voltage below 0.5 V is due to the small diameter and carrier concentration of channel.•Both normally-off and good off-state performances are achieved from gate-all-around structure of channel.•GaN vertical nanowire MOSFET is also promising for low voltage logic applications. GaN gate-all-around (GAA) vertical nanowire MOSFET (VNWMOSFET) with channel length of 300 nm and diameter of 120 nm, the narrowest GaN-based vertical nanowire transistor ever achieved from the top-down approach, was fabricated by utilizing anisotropic side-wall wet etching in TMAH solution and photoresist etch-back process. The VNWMOSFET exhibited output characteristics with very low saturation drain voltage of less than 0.5 V, which is hardly observed from the wide bandgap-based devices. Simulation results indicated that the narrow diameter of the VNWMOSFET with relatively short channel length is responsible for the low voltage operation. The VNWMOSFET also demonstrated normally-off mode with threshold voltage (VTH) of 0.7 V, extremely low leakage current of ∼10−14 A, low drain-induced barrier lowering (DIBL) of 125 mV/V, and subthreshold swing (SS) of 66–122 mV/decade. The GaN GAA VNWMOSFET with narrow channel diameter investigated in this work would be promising for new low voltage logic application.