Low frequency noise investigation of n-MOSFET single cells for memory applications

• Published in: Solid-state electronics 2019-01, Vol.151, p.36-39
• Main Authors: Ioannidis, E.G., Leisenberger, F.P., Enichlmair, H.
• Format: Article
• Language: English
• Subjects: CMOS; Logic NVM; Low frequency noise; n-MOSFET
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2018.10.016

•This paper investigates the impact on low frequency noise of n-MOSFET dedicated for memory applications.•We analyze the impact of different gate oxide thickness and LDD composition in source/drain side on LFN performance. In this paper, we present a detailed investigation of low frequency noise (LFN) for different n-MOSFET devices dedicated for memory applications. We investigate the impact of the gate oxide thickness (GOX) on LFN. We analyzed how the position, the existence and the composition of Lightly Doped Dopant (LDD) implant in the source/drain region affect the LFN performance of the device. The results demonstrates that the thinner gate oxide and the device without LDD improved the noise performance compared the devices with thick GOX and with LDD implants. On the other hand, the absence of LDD implant on one side of the MOSFET didn’t reveal a global trend for all measured devices. Finally, the different LDD implant composition resulted in different LFN performance which is gate area dependent. These results can be used from both process and design engineers to improve the LFN of n-MOSFET.