Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs

• Published in: Solid-state electronics 2021-10, Vol.184, p.108087, Article 108087
• Main Authors: Simoen, Eddy, de Oliveira, Alberto Vinicius, Agopian, Paula Ghedini Der, Ritzenthaler, Romain, Mertens, Hans, Horiguchi, Naoto, Martino, Joao Antonio, Claeys, Cor, Veloso, Anabela
• Format: Article
• Language: English
• Subjects: Gate-All-Around; Low-frequency noise; Nanosheets; Nanowires; Silicon MOSFETs
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2021.108087

•LF noise in 3 generations of silicon nanowire transistors.•New results in vertical NW transistors.•Impact of gate stack processing on the 1/f noise magnitude. The low frequency noise performance of Gate-All-Around Nanowire (NW) or Nanosheet (NS) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is investigated, taking account of the impact of the device architecture, i.e., junctionless (JL) versus inversion-mode (IM) and process variations for the gate metal. The horizontal devices are characterized by 1/f noise, dominated by the number fluctuation mechanism, so that the power spectral density (PSD) is directly proportional with the trap density in the gate stack. The average 1/f noise PSD is becoming smaller going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices on bulk silicon and, finally, vertical NWFETs with a substrate source contact. At low currents and frequencies below 1 kHz the 1/f noise in the vertical NWs is, in contrast to the horizontal devices, controlled by mobility fluctuations. In these devices white noise is observed above 1 kHz.