Current-to-transconductance ratio technique for simultaneous extraction of threshold voltage and parasitic resistances in MOSFETs

•Simple technique for simultaneously extracting RD, RS, and VT of MOSFET is presented.•This technique is applicable to any single MOSFET with CLM and structural asymmetry.•The validity of the proposed technique is demonstrated experimentally. In this work, a current-to-transconductance ratio techniq...

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Bibliographic Details
Published in:Solid-state electronics 2021-09, Vol.183, p.108133, Article 108133
Main Authors: Kim, Haesung, Yoo, Han Bin, Ryu, Ji Hee, Bae, Jong-Ho, Choi, Sung-Jin, Kim, Dae Hwan, Kim, Dong Myong
Format: Article
Language:English
Subjects:
Drain resistance
MOSFET
Parasitic resistance
Separate extraction
Source resistance
Threshold voltage
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Summary:•Simple technique for simultaneously extracting RD, RS, and VT of MOSFET is presented.•This technique is applicable to any single MOSFET with CLM and structural asymmetry.•The validity of the proposed technique is demonstrated experimentally. In this work, a current-to-transconductance ratio technique is proposed for simultaneous extraction of the threshold voltage (VT) and parasitic source (RS) and drain (RD) resistances in short channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed technique allows simultaneous extraction of RS, RD, and VT in any single MOSFET with the channel length modulation (CLM) and the structural asymmetry. The proposed method is experimentally verified through Si MOSFETs with intentional asymmetry by connecting an external resistor (Rext) to the source terminal. We experimentally confirmed that extracted RS, RD, and VT are independent of the drain bias (VDS) and intentional Rext employed for the asymmetry. We also compared the results with previously reported techniques.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2021.108133