Study of gate current in advanced MOS architectures

We have carried out a comprehensive study of the gate current (IG) in advanced MOS architectures for different gate lengths and cross-section areas using an in–house simulation tool. We have considered only direct tunneling under the assumption that trap concentration and therefore the trap assisted...

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Bibliographic Details
Published in:Solid-state electronics 2022-08, Vol.194, p.108345, Article 108345
Main Authors: Gauhar, Ghulam Ali, Chenchety, Abhishek, Yenugula, Hashish, Georgiev, Vihar, Asenov, Asen, Badami, Oves
Format: Article
Language:English
Subjects:
Gate current
Tunneling
WKB Approximation
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Summary:We have carried out a comprehensive study of the gate current (IG) in advanced MOS architectures for different gate lengths and cross-section areas using an in–house simulation tool. We have considered only direct tunneling under the assumption that trap concentration and therefore the trap assisted current would be small in a matured technology. We have also studied the impact of the interfacial (IL) SiO2 layer on the gate current in the high-κ gate stack. Our results suggest that IL leads to an increase in the gate current for equivalent EOT. They also highlight that reduction in the cross-section area leads to a significant increase in the IG.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2022.108345