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Negative capacitance field-effect transistor with hetero-dielectric structure for suppression of reverse drain induced barrier lowering

•There is an undesirable phenomenon called Reverse Drain induced Barrier Lowering (RDIBL) in NCFETs, which causes SS degradation and Ion reduction.•A new NCFET device structure with hetero-dielectric (HD-NCFET) is proposed to improve the RDIBL phenomenon.•The HD-NCFET can be a candidate for the futu...

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Bibliographic Details
Published in:Solid-state electronics 2023-05, Vol.203, p.108581, Article 108581
Main Authors: Kim, Dong-Oh, Lee, Kitae, Kim, Changha, Kim, Sihyun, Kim, Hyun-Min, Kwon, Daewoong, Park, Byung-Gook
Format: Article
Language:English
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Summary:•There is an undesirable phenomenon called Reverse Drain induced Barrier Lowering (RDIBL) in NCFETs, which causes SS degradation and Ion reduction.•A new NCFET device structure with hetero-dielectric (HD-NCFET) is proposed to improve the RDIBL phenomenon.•The HD-NCFET can be a candidate for the future generation NCFET as long as hetero-dielectric is finely controlled. Recently, negative capacitance FETs (NCFET) using ferroelectric materials as a gate oxide have received much attention as one of the candidates for next-generation low power/high-performance devices because they can have sub-60 mV/dec subthreshold swing at room temperature through the channel potential amplification. However, the reverse drain induced barrier lowering phenomenon occurs by the local rising of the drain-side conduction energy band when a high drain voltage is applied to NCFETs, leading to the degradation of on-current and subthreshold swing. In this work, a novel NCFET with hetero-dielectric (HD-NCFET), where the gate dielectric consists of source-side ferroelectric material and drain-side paraelectric silicon dioxide (SiO2), is proposed to prevent the undesirable reverse drain induced barrier lowering phenomenon. Through technology computer-aided design simulations, the effects of operating voltage and SiO2 length on the electrical characteristics of the HD-NCFET are rigorously analyzed to optimize and maximize its device performance.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2022.108581