CARAT – A reliability analysis framework for BTI-HCD aging in circuits

•Circuit Aging Reliability Analysis Tool (CARAT) framework building.•Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) induced degradation of FETs calculation in actual circuits using inbuilt models.•Activity Awareness under random data-path.•Dynamic Voltage Frequency Scaling(DVFS...

Full description

Saved in:
Bibliographic Details
Published in:Solid-state electronics 2023-03, Vol.201, p.108586, Article 108586
Main Authors: Gholve, Prasad, Chatterjee, Payel, Pasupuleti, Chaitanya, Amrouch, Hussam, Gangwar, Narendra, Das, Shouvik, Sharma, Uma, van Santen, Victor M., Mahapatra, Souvik
Format: Article
Language:English
Subjects:
Activity awareness
BTI
DVFS
HCD
HSPICE
Level Shifter
Ring Oscillator
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:•Circuit Aging Reliability Analysis Tool (CARAT) framework building.•Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) induced degradation of FETs calculation in actual circuits using inbuilt models.•Activity Awareness under random data-path.•Dynamic Voltage Frequency Scaling(DVFS) using Ring Oscillator(RO) Circuit Aging Reliability Analysis Tool (CARAT), a framework that calculates random activity (frequency and duty) aware degradation of FETs to simulate circuit aging under real operating workloads is proposed. Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) induced degradation of FETs is calculated in a cycle-by-cycle manner based on actual terminal waveforms grabbed from SPICE. Framework capability is demonstrated by using Level Shifter (LS) under random data-path activity, and Ring Oscillator (RO) under Dynamic Voltage Frequency Scaling (DVFS) conditions. The risk associated with the standard blanket approach is discussed.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2022.108586