Ultra low power offering 14 nm bulk double gate FinFET based SRAM cells

• Published in: Sustainable computing informatics and systems 2022-09, Vol.35, p.100685, Article 100685
• Main Authors: M., Damodhar Rao, Y.V., Narayana, V.V.K.D.V., Prasad
• Format: Article
• Language: English
• Subjects: FEM tool; FinFET; Leakage currents; MOSFET; SRAM cells
• ISSN: 2210-5379
• DOI: 10.1016/j.suscom.2022.100685

•The high-k dielectric material, HfO2 as oxide layer in FinFET device, reduces the leakage current and threshold voltages.•The bulk double gate FinFET has less hot carrier injection and provides good control on channel.•A 14nm bulk double gate FinFET based SRAM cell is designed and implemented in 6T, 7T, 8T and 9T topologies.•The detailed comparative analysis helps in memory design of smart phones, IoT based systems, etc. For many decades, SRAM cell design with low power dissipation is the problem of interest for researchers due to its numerous applications in embedded systems. In this research work, a Bulk double gate FinFET based design of SRAM cell and performance analysis is carried out. Also, a comprehensive analysis is performed on FinFET and CMOS technology based SRAM cells. The novelty in the proposed work is, the designing of the 14 nm bulk double gate FinFET transistor using the FEM tool and eventually designing the SRAM cells. The designed bulk FinFET offers an IDS of 3.5 μA/μm with HfO2 as dielectric material. By using this type of FinFET in SRAM cell design the leakage current is reduced significantly. The performance analysis on 6 T(T represents the number of transistors used in the design of SRAM cell), 7 T, 8 T and 9 T SRAM cells design with MOSFET and FinFET technologies is done in terms of leakage current, power dissipation and static noise margin. Compared with MOSFET, FinFET based SRAM cell offers low leakages especially 7 T SRAM cell has low leakage of 296.7 pW. The SRAM cells SNM value is also improved by 10 %.