Interconnect support for energy efficient and high bandwidth memory access in CMPs

• Published in: Sustainable computing informatics and systems 2022-04, Vol.34, p.100720, Article 100720
• Main Authors: Mondal, Hemanta Kumar, Konar, Sarnava, Hore, Poulomi, Patra, Ramapati, Sarkar, Pradipta, Deb, Sujay
• Format: Article
• Language: English
• Subjects: Drowsy circuit and Power gating; Hybrid switching; Machine learning; Network-on-Chip; Optimal placement
• ISSN: 2210-5379
• DOI: 10.1016/j.suscom.2022.100720

The increasing number of on-chip cores and a limited number of memory controllers pose a critical problem for off-chip memory bandwidth. In this work, we propose an adaptive hybrid switching strategy with a dual crossbar router to provide low latency paths between cache and memory controllers. The performance is further improved by finding the optimal number and placement of memory controllers using machine learning approach with low overheads. The proposed architecture improves the average bandwidth of the network by 21.03% and reduces the network energy and memory access latency by 12.60% and 20.45%, respectively as compared to the traditional NoC architecture. •A hybrid switching strategy with dual crossbar routers that allow simultaneous use of both circuit and packet-switched paths.•An optimal number and placement of memory controllers in the network using machine learning approach.•An energy-efficient router architecture using power-efficient drowsy and power-gating techniques.•New experimental evaluations with various application-specific traffic scenarios in terms of throughput, latency, improvements.•A detailed analysis of scalability and a summary of proposed and existing works