Low power content addressable memory designing and implementation using voltage swing self adjustable match line technique

• Published in: Sustainable computing informatics and systems 2024-09, Vol.43, p.101002, Article 101002
• Main Authors: Inamanamelluri, Saidulu, Dhanasekaran, D., Bhaskar, Radhika
• Format: Article
• Language: English
• Subjects: Content addressable memory (CAM); Match-line sensing; Self-adjustable match-line; Voltage swing
• ISSN: 2210-5379
• DOI: 10.1016/j.suscom.2024.101002

One of the essential components of computer systems is memory. A primary hindrance in this regard is the memory speed. Content Addressable Memory (CAM) speeds up transformations and table lookups in network routers and data processing systems for hardware search engines. Parallel seeks using the CAM (Content Addressable Memory) model are often used to enhance memory performance. This paper uses the voltage swing self-adjustable match line (VSSA-ML) technique to describe low-power content addressable memory design and implementation. This project decreases Match Line (ML) power loss by reducing load capacitance and ML voltage swing. A simple ML voltage detector is proposed instead of the complex, fully different detector that allows ML voltage swings near zero. This paper presents 6 T 8×8 CAM arrays using VSSA-ML Technique using Tanner tools 45-nm technology. On the other hand, this design enhances robustness in processing variations by self-adjusting voltage swings. Implementation analysis states that the described mode 6 T 8×8 CAM design utilized fewer MOSFETs than the 8 T 8×8 CAM array. •VSSA-ML: Innovative technique for Low Power CAM design.•Reduces ML power loss via load capacitance & voltage control.•Simple ML voltage detector enables near-zero voltage swings.•Implemented in 45nm using Tanner tools, proving feasibility.•Enhances CAM robustness to process variations autonomously.