High aspect ratio via etch development for Cu nails in 3-D-stacked ICs

In this study the etch development of high aspect ratio vias in Si for the fabrication of Cu nails is described. To enable subsequent metallisation, these vias need to meet strict requirements with respect to uniformity, slope, sidewall roughness and undercut. For aspect ratios up to 5 a SiO 2 hard...

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Bibliographic Details
Published in:Thin solid films 2008-04, Vol.516 (11), p.3502-3506
Main Authors: Van Aelst, J., Struyf, H., Boullart, W., Vanhaelemeersch, S.
Format: Article
Language:English
Subjects:
3-D via etch
Applied sciences
Bosch
Deep Si etch
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
High aspect ratio
Integrated circuits
Microelectronic fabrication (materials and surfaces technology)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Summary:In this study the etch development of high aspect ratio vias in Si for the fabrication of Cu nails is described. To enable subsequent metallisation, these vias need to meet strict requirements with respect to uniformity, slope, sidewall roughness and undercut. For aspect ratios up to 5 a SiO 2 hard mask based SF6/O 2 etch approach is used. For aspect ratios up to 10, a resist based passivation polymer type etch approach with C4F8/SF6 was used to successfully pattern vias in Si. Typical problems of this process and optimization to overcome the issues are described.
ISSN:0040-6090
1879-2731
DOI:10.1016/j.tsf.2007.08.079