High-gain and low-hysteresis properties of organic inverters with an UV-photo patternable gate dielectrics

• Published in: Thin solid films 2008-04, Vol.516 (12), p.4330-4333
• Main Authors: Lim, Sang Chul, Kim, Seong Hyun, Kim, Gi Heon, Koo, Jae Bon, Yang, Yong Suk, Lee, Jung Hun, Ku, Chan Hoe, Song, Yoon-Ho
• Format: Article
• Language: English
• Subjects: Applied sciences; Condensed matter: electronic structure, electrical, magnetic, and optical properties; Electrical properties of specific thin films; Electronic structure and electrical properties of surfaces, interfaces, thin films and low-dimensional structures; Electronics; Exact sciences and technology; Gate dielectrics; Hysteresis; Inverter; Organic thin-film transistors; Pentacene; Physics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors
• ISSN: 0040-6090; 1879-2731
• DOI: 10.1016/j.tsf.2007.12.134

Low-hysteresis properties for an organic thin-film transistor (OTFTs) and a high-gain inverter were fabricated using a self-synthesized UV-photo patternable gate dielectric. The hysteresis behavior was not observed in the transfer characteristics of OTFTs or in the voltage transfer characteristics of the organic inverter. For a given dielectric thickness and applied voltage, pentacene OTFTs with inverter circuits were characterized by the field effect mobility, the on/off current ratio, threshold voltage (V th), and the gain. The field effect mobility, V th and the on/off currents ratio were 0.03 cm 2/Vs,− 3.3 V and 10 6, respectively. The inverter has very large gain of 32 and matching input and output levels, despite having a positive switch-on voltage and slight hysteresis. From OTFT device and inverter circuit measurements, it was found that the hysteresis behavior was caused by the interface-state charge trapping between the gate dielectric and the pentacene semiconductor layer.