Ge wire MOSFETs fabricated by three-dimensional Ge condensation technique

• Published in: Thin solid films 2008-11, Vol.517 (1), p.167-169
• Main Authors: Irisawa, T., Numata, T., Hirashita, N., Moriyama, Y., Nakaharai, S., Tezuka, T., Sugiyama, N., Takagi, S.
• Format: Article
• Language: English
• Subjects: Applied sciences; Cross-disciplinary physics: materials science; rheology; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Ge condensation; Ge on insulator (GOI); Integrated circuits; Materials science; Methods of nanofabrication; MOSFET; Nano-wire; Nanoscale materials and structures: fabrication and characterization; Physics; Quantum wires; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SiGe; SiGe on insulator (SGOI); Transistors
• ISSN: 0040-6090; 1879-2731
• DOI: 10.1016/j.tsf.2008.08.054

We propose a novel method to form Ge nano-wire structures by utilizing a three-dimensional (3D) Ge condensation technique. Since this method needs only top-down and Si compatible processes, Ge nano-wire MOSFETs fabricated by this technique are suitable for actual LSI applications. Based on this concept, we have fabricated SiGe on insulator wire pMOSFETs with Ge content up to 92% and diameter down to 35 nm. 3× enhancement of transconductance against a control Si device has been demonstrated in pMOSFETs with Ge content of 79%, though the performance enhancement in the highest Ge content device has not been obtained yet because of the non-optimized 3D Ge condensation processes. Further performance enhancement is expected after optimizing 3D Ge condensation processes especially for higher Ge content SiGe channels.