Novel logic and memory synthesis algorithm for Memristive Hardware Description Language (HDL)

• Published in: Integration (Amsterdam) 2024-05, Vol.96, p.102140, Article 102140
• Main Authors: Ng, L.S., Phan, K.Y., Ho, Patrick W.C.
• Format: Article
• Language: English
• Subjects: Hardware Description Language; Logic synthesis; Memory synthesis; Memristor; Netlist
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2024.102140

—The fourth basic circuit element, known as the memristor, renowned for its small size, and ability to store and retain information as resistance, allowing for implementation for logic circuits such as logic gates or memory cells. The memristor allows the development of small-scale electronics as a continuation of CMOS technology, which is rapidly approaching its limit due to Moore's Law. Currently, there has not been much development into the design automation of circuit utilizing memristors, which makes the designing of complex, large-scale circuits with memristors considerably difficult. At hitherto, there is only a generic framework for memristor netlist generation, mapping and routing. However, current literature shows a lack of logic optimizer and memristor circuit synthesizer. Hence, this article proposes a Novel Logic Synthesis Algorithm for Memristive Hardware Description Language (HDL). The synthesis algorithm proposed in this article extracts Verilog conditional statements and registers, optimizes the circuit and synthesizes into a suitable memristor circuits in netlist form.