On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity

• Published in: Integration (Amsterdam) 2024-07, Vol.97, p.102175, Article 102175
• Main Authors: Dhiman, Saurabh, Shrimali, Hitesh
• Format: Article
• Language: English
• Subjects: Charge; Charge compensation; Charge injection; Clock-feedthrough; Dummy switch; MOS switch; Switched-capacitor; Track-and-hold
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2024.102175

The paper proposes an ameliorated methodology to minimize the effect of charge injection over a wide input common-mode range. Instead of a conventional single dummy switch compensation [1], the multi-dummy switches are proposed and employed to eradicate the injected charge on to the sampling capacitor. A detailed methodology is presented to compensate the charge injection in a MOS switch. The closed-form equations are derived mathematically to substantiate the proposed technique. For the proof-of-concept, a track-and-hold (T/H) stage has been simulated in 0.18μm CMOS technology with the proposed technique for a 10-bit resolution. The proposed technique based T/H stage exhibits the spurious free dynamic range (SFDR) of 62.6 dB, effective number of bits (ENOB) of 9.36, peak input-referred third-order intercept point (IIP3) of 13.02 dBm and an input-referred 1 dB compression point (P1dB) of 3.8 dBm at 1.074 MHz input frequency, sampled at 100 MSa/s. The performance of the proposed method is compared with the existing single dummy switch compensation method where our technique shows 88.8% compensation in minimizing the charge injection error and 272% improvement in dynamic linearity. Moreover, the presented technique quantifies 9× improvement in mean percentage error (MPE) when simulated across the various process corners and rail-to-rail input common-mode voltage. •The paper presents a multi-dummy switch technique to minimize the charge injection error in a MOS switch.•Mathematical analysis has been carried out to validate the concept.•A design methodology is proposed to limit the charge injection error within ±0.5 LSB for 10-bit track-and-hold circuit.•The presented method is compared with existing single dummy switch compensation technique and the results depict 272% improvement in dynamic linearity.•The proposed method provides 9X improvement in the mean percentage error over the existing method.•The design is simulated in CMOS 180 nm technology and the post-layout simulation results are reported in the paper.