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Contact Resistance Engineering in WS 2 -Based FET with MoS 2 Under-Contact Interlayer: A Statistical Approach

One of the primary factors hindering the development of 2D material-based devices is the difficulty of overcoming fabrication processes, which pose a challenge in achieving low-resistance contacts. Widely used metal deposition methods lead to unfavorable Fermi level pinning effect (FLP), which preve...

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Bibliographic Details
Published in:ACS applied materials & interfaces 2024-09, Vol.16 (36), p.48556-48564
Main Authors: Giza, Małgorzata, Świniarski, Michał, Gertych, Arkadiusz P, Czerniak-Łosiewicz, Karolina, Rogala, Maciej, Kowalczyk, Paweł J, Zdrojek, Mariusz
Format: Article
Language:English
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Summary:One of the primary factors hindering the development of 2D material-based devices is the difficulty of overcoming fabrication processes, which pose a challenge in achieving low-resistance contacts. Widely used metal deposition methods lead to unfavorable Fermi level pinning effect (FLP), which prevents control over the Schottky barrier height at the metal/2D material junction. We propose to harness the FLP effect to lower contact resistance in field-effect transistors (FETs) by using an additional 2D interlayer at the conducting channel and metallic contact interface (under-contact interlayer). To do so, we developed a new approach using the gold-assisted transfer method, which enables the fabrication of heterostructures consisting of TMDs monolayers with complex shapes, prepatterned using e-beam lithography, with lateral dimensions even down to 100 nm. We designed and demonstrated tungsten disulfide (WS ) monolayer-based devices in which the molybdenum disulfide (MoS ) monolayer is placed only in the contact area of the FET, creating an Au/MoS /WS junction, which effectively reduces contact resistance by over 60% and improves the / ratio 10 times in comparison to WS -based devices without MoS under-contact interlayer. The enhancement in the device operation arises from the FLP effect occurring only at the interface between the metal and the first layer of the MoS /WS heterostructure. This results in favorable band alignment, which enhances the current flow through the junction. To ensure the reproducibility of our devices, we systematically analyzed 160 FET devices fabricated with under-contact interlayer and without it. Statistical analysis shows a consistent improvement in the operation of the device and reveals the impact of contact resistance on key FET performance indicators.
ISSN:1944-8244
1944-8252
DOI:10.1021/acsami.4c09688