Extraction of interface state density profile from the maximums of the parallel conductance versus applied gate bias curves G p (Va), using the conductance technique

A fast method for extracting the interface trap density profile of the semiconductor‐insulator interface in metal‐insulator‐semiconductor structures is proposed. The method is based on the well known conductance technique and extracts the interface state density profile from the maximums of the para...

Full description

Saved in:
Bibliographic Details
Published in:Review of scientific instruments 1992-09, Vol.63 (9), p.4189-4191
Main Authors: Papadas, C., Morfouli, P., Ghibaudo, G., Pananakakis, G.
Format: Article
Language:English
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A fast method for extracting the interface trap density profile of the semiconductor‐insulator interface in metal‐insulator‐semiconductor structures is proposed. The method is based on the well known conductance technique and extracts the interface state density profile from the maximums of the parallel conductance versus applied gate bias curves, G p (V a ). In addition, this method is directly applicable to fully automated experimental setups available in industrial environments.
ISSN:0034-6748
1089-7623
DOI:10.1063/1.1143232