Fabrication of Si single-electron transistors having double SiO2 barriers

We fabricated Si single-electron transistors (SETs) having double SiO2 barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned betw...

Full description

Saved in:
Bibliographic Details
Published in:Applied physics letters 2002-06, Vol.80 (24), p.4617-4619
Main Authors: Ito, Yuhei, Hatano, Tsuyoshi, Nakajima, Anri, Yokoyama, Shin
Format: Article
Language:English
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c359t-a711d305e3f88ce455bc4218504e1e20768458debb0c2648bafdbd22e790e9f73
cites cdi_FETCH-LOGICAL-c359t-a711d305e3f88ce455bc4218504e1e20768458debb0c2648bafdbd22e790e9f73
container_end_page 4619
container_issue 24
container_start_page 4617
container_title Applied physics letters
container_volume 80
creator Ito, Yuhei
Hatano, Tsuyoshi
Nakajima, Anri
Yokoyama, Shin
description We fabricated Si single-electron transistors (SETs) having double SiO2 barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned between the source and drain regions. The device exhibits drain current (Id) oscillation against gate voltage. From the dot size dependence of the electrical characteristics, the Id oscillation is considered to be due to the Coulomb blockade effect caused by poly-Si grains in the poly-Si dot. The self-alignment of the poly-Si dot in the fabrication process also means that the SET is promising for practical use.
doi_str_mv 10.1063/1.1485306
format article
fullrecord <record><control><sourceid>crossref</sourceid><recordid>TN_cdi_crossref_primary_10_1063_1_1485306</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>10_1063_1_1485306</sourcerecordid><originalsourceid>FETCH-LOGICAL-c359t-a711d305e3f88ce455bc4218504e1e20768458debb0c2648bafdbd22e790e9f73</originalsourceid><addsrcrecordid>eNotkEtLxDAUhYMoWEcX_oNsXXS8N48mXcrg6MDALNR1SdIbjdRWkir47604q8N5cBYfY9cIa4RG3uIaldUSmhNWIRhTS0R7yioAkHXTajxnF6W8L1YLKSu22zqfU3BzmkY-Rf6UeEnj60A1DRTmvKRzdmNJZZ5y4W_ue2l5P335gZbxQXDvck6UyyU7i24odHXUFXvZ3j9vHuv94WG3udvXQep2rp1B7CVoktHaQEprH5RAq0ERkgDTWKVtT95DEI2y3sXe90KQaYHaaOSK3fz_hjyVkil2nzl9uPzTIXR_DDrsjgzkLxuhTjQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Fabrication of Si single-electron transistors having double SiO2 barriers</title><source>American Institute of Physics (AIP) Publications</source><source>American Institute of Physics:Jisc Collections:Transitional Journals Agreement 2021-23 (Reading list)</source><creator>Ito, Yuhei ; Hatano, Tsuyoshi ; Nakajima, Anri ; Yokoyama, Shin</creator><creatorcontrib>Ito, Yuhei ; Hatano, Tsuyoshi ; Nakajima, Anri ; Yokoyama, Shin</creatorcontrib><description>We fabricated Si single-electron transistors (SETs) having double SiO2 barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned between the source and drain regions. The device exhibits drain current (Id) oscillation against gate voltage. From the dot size dependence of the electrical characteristics, the Id oscillation is considered to be due to the Coulomb blockade effect caused by poly-Si grains in the poly-Si dot. The self-alignment of the poly-Si dot in the fabrication process also means that the SET is promising for practical use.</description><identifier>ISSN: 0003-6951</identifier><identifier>EISSN: 1077-3118</identifier><identifier>DOI: 10.1063/1.1485306</identifier><language>eng</language><ispartof>Applied physics letters, 2002-06, Vol.80 (24), p.4617-4619</ispartof><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c359t-a711d305e3f88ce455bc4218504e1e20768458debb0c2648bafdbd22e790e9f73</citedby><cites>FETCH-LOGICAL-c359t-a711d305e3f88ce455bc4218504e1e20768458debb0c2648bafdbd22e790e9f73</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,782,784,27924,27925</link.rule.ids></links><search><creatorcontrib>Ito, Yuhei</creatorcontrib><creatorcontrib>Hatano, Tsuyoshi</creatorcontrib><creatorcontrib>Nakajima, Anri</creatorcontrib><creatorcontrib>Yokoyama, Shin</creatorcontrib><title>Fabrication of Si single-electron transistors having double SiO2 barriers</title><title>Applied physics letters</title><description>We fabricated Si single-electron transistors (SETs) having double SiO2 barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned between the source and drain regions. The device exhibits drain current (Id) oscillation against gate voltage. From the dot size dependence of the electrical characteristics, the Id oscillation is considered to be due to the Coulomb blockade effect caused by poly-Si grains in the poly-Si dot. The self-alignment of the poly-Si dot in the fabrication process also means that the SET is promising for practical use.</description><issn>0003-6951</issn><issn>1077-3118</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><recordid>eNotkEtLxDAUhYMoWEcX_oNsXXS8N48mXcrg6MDALNR1SdIbjdRWkir47604q8N5cBYfY9cIa4RG3uIaldUSmhNWIRhTS0R7yioAkHXTajxnF6W8L1YLKSu22zqfU3BzmkY-Rf6UeEnj60A1DRTmvKRzdmNJZZ5y4W_ue2l5P335gZbxQXDvck6UyyU7i24odHXUFXvZ3j9vHuv94WG3udvXQep2rp1B7CVoktHaQEprH5RAq0ERkgDTWKVtT95DEI2y3sXe90KQaYHaaOSK3fz_hjyVkil2nzl9uPzTIXR_DDrsjgzkLxuhTjQ</recordid><startdate>20020617</startdate><enddate>20020617</enddate><creator>Ito, Yuhei</creator><creator>Hatano, Tsuyoshi</creator><creator>Nakajima, Anri</creator><creator>Yokoyama, Shin</creator><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20020617</creationdate><title>Fabrication of Si single-electron transistors having double SiO2 barriers</title><author>Ito, Yuhei ; Hatano, Tsuyoshi ; Nakajima, Anri ; Yokoyama, Shin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c359t-a711d305e3f88ce455bc4218504e1e20768458debb0c2648bafdbd22e790e9f73</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2002</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ito, Yuhei</creatorcontrib><creatorcontrib>Hatano, Tsuyoshi</creatorcontrib><creatorcontrib>Nakajima, Anri</creatorcontrib><creatorcontrib>Yokoyama, Shin</creatorcontrib><collection>CrossRef</collection><jtitle>Applied physics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Ito, Yuhei</au><au>Hatano, Tsuyoshi</au><au>Nakajima, Anri</au><au>Yokoyama, Shin</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Fabrication of Si single-electron transistors having double SiO2 barriers</atitle><jtitle>Applied physics letters</jtitle><date>2002-06-17</date><risdate>2002</risdate><volume>80</volume><issue>24</issue><spage>4617</spage><epage>4619</epage><pages>4617-4619</pages><issn>0003-6951</issn><eissn>1077-3118</eissn><abstract>We fabricated Si single-electron transistors (SETs) having double SiO2 barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned between the source and drain regions. The device exhibits drain current (Id) oscillation against gate voltage. From the dot size dependence of the electrical characteristics, the Id oscillation is considered to be due to the Coulomb blockade effect caused by poly-Si grains in the poly-Si dot. The self-alignment of the poly-Si dot in the fabrication process also means that the SET is promising for practical use.</abstract><doi>10.1063/1.1485306</doi><tpages>3</tpages><oa>free_for_read</oa></addata></record>
fulltext fulltext
identifier ISSN: 0003-6951
ispartof Applied physics letters, 2002-06, Vol.80 (24), p.4617-4619
issn 0003-6951
1077-3118
language eng
recordid cdi_crossref_primary_10_1063_1_1485306
source American Institute of Physics (AIP) Publications; American Institute of Physics:Jisc Collections:Transitional Journals Agreement 2021-23 (Reading list)
title Fabrication of Si single-electron transistors having double SiO2 barriers
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T18%3A30%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Fabrication%20of%20Si%20single-electron%20transistors%20having%20double%20SiO2%20barriers&rft.jtitle=Applied%20physics%20letters&rft.au=Ito,%20Yuhei&rft.date=2002-06-17&rft.volume=80&rft.issue=24&rft.spage=4617&rft.epage=4619&rft.pages=4617-4619&rft.issn=0003-6951&rft.eissn=1077-3118&rft_id=info:doi/10.1063/1.1485306&rft_dat=%3Ccrossref%3E10_1063_1_1485306%3C/crossref%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c359t-a711d305e3f88ce455bc4218504e1e20768458debb0c2648bafdbd22e790e9f73%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true