Tunneling discharge of positive trapped oxide charge in p-channel field effect transistors

Negative bias temperature instability has been studied in 130 nm and 90 nm channel length, SiO 2 gate insulator field effect transistors at room temperature. Pulsed voltage stressing and subsequent recovery using times starting in the tens of microsecond regime were employed together with a single p...

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Bibliographic Details
Published in:Applied physics letters 2011-08, Vol.99 (8), p.083506-083506-3
Main Authors: Kambour, K. E., Kouhestani, C., Nguyen, D., Rosen, N., Devine, R. A. B.
Format: Article
Language:English
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Summary:Negative bias temperature instability has been studied in 130 nm and 90 nm channel length, SiO 2 gate insulator field effect transistors at room temperature. Pulsed voltage stressing and subsequent recovery using times starting in the tens of microsecond regime were employed together with a single point data acquisition time ∼4 μ s. Threshold voltage shifts were characteristic of oxide charge trapping as opposed to interface state generation. Recovery of the threshold voltage was modeled assuming quantum mechanical tunneling of trapped charges from the dielectric to the Si substrate.
ISSN:0003-6951
1077-3118
DOI:10.1063/1.3628462