Highly-matched sub-ADC cells for pipeline analogue-to-digital converters

• Published in: International journal of electronics 2019-12, Vol.106 (12), p.1785-1813
• Main Authors: Kazeminia, S., Mahdavi, Sina
• Format: Article
• Language: English
• Subjects: Analog to digital conversion; Analog to digital converters; Basic converters; CMOS; Comparators; Computer simulation; high-resolution pipeline ADCs; highly-matched comparators; input-referred offset; Metal oxide semiconductors; Monte Carlo simulation; Negative feedback; Normal distribution; offset cancelled comparators; Pipelines; Power consumption; Single-Stage Comparators
• ISSN: 0020-7217; 1362-3060
• DOI: 10.1080/00207217.2019.1625969

The conventional single-stage comparators, as the basic elements of analogue-to-digital converters (ADCs), are modified for offset and mismatch errors to be utilised in multi-bit per stage pipeline structures. At first, in single-stage comparators, pre-amplification and latch operations are managed by temporary domination of positive or negative feedback via the bulk potential variations in PMOS (p-channel metal oxide semiconductor) devices. Then, the offset correction scheme is added to provide highly matched unit cells within the sub-ADCs of the pipeline structure. Monte-Carlo analysis with 100 iterations shows that input-referred offset reduces to 0.35 mV at σ, while input offset was randomly applied from a Gaussian distribution with 30 mV at 3σ. Using as unit cells of sub-ADCs in a 12-bit 100 MS/s pipeline ADC, ENOB (and SFDR) would be improved from 8.5-bits (and 53.6 dB) to 11.25-bits (and 74.2 dB), when offset error and bulk potential of PMOS devices experiences random variations with 25 mV and 60 mV at 3σ, respectively. Power consumption reaches to 0.45 mW at 625MS/s comparison speed. Post-Layout simulation results are presented at all process corners using the BSIM3v3 model of a 0.18 µm CMOS technology.